Is EUV Overhyped? Erik Hosler Talks Real Innovation in Chip Scaling

Extreme Ultraviolet (EUV) lithography was long viewed as Moore’s Law’s redeeming quality. By enabling finer feature resolution with shorter wavelengths, EUV offered chipmakers the most advanced path forward when traditional scaling methods began to falter. Yet today, the EUV is not the full answer to sustaining semiconductor progress. Erik Hosler, a semiconductor strategist with deep involvement in lithographic systems and process roadmap alignment, understands that preserving momentum will require far more than just refining a single tool.

While EUV remains crucial for enabling advanced nodes, it is only one component in a broader effort to extend chip performance, efficiency, and density. Progress now depends on complementary innovations in materials, packaging, metrology, photonics, MEMS, and design automation. It is this collective push, rather than any one breakthrough, that will define the next era of Moore’s Law.

EUV’s Capabilities and Its Limitations

EUV lithography operates at a wavelength of 13.5 nanometers, far shorter than Deep Ultraviolet (DUV) tools. It allows it to print finer features with fewer patterning steps. In practice, this means better performance, smaller chips, and reduced complexity for certain critical layers. Leading chipmakers have adopted EUV in high-volume manufacturing, and next-generation High Numerical Aperture (high-NA) EUV tools are under development.

But EUV is not without its issues. Source power limitations, line-edge roughness, stochastic printing errors, and photomask defects continue to impact process reliability. Photoresist development has also struggled to keep pace, with many materials failing to provide the resolution, sensitivity, and stability needed at scale. Solving these challenges requires more than simply better EUV tools. It requires breakthroughs across chemistry, metrology, simulation, and system integration.

Beyond Lithography: A Broader Landscape of Solutions

At the SPIE Advanced Lithography symposium, the recurring message was clear that sustaining Moore’s Law is no longer a singular path. Developments in adjacent sectors must support each gain in lithography.

EUV alone will not address the power and efficiency requirements of artificial intelligence workloads, nor will it reduce the latency in massive data centers or enable real-time responsiveness in edge devices. These demands require architectural redesign, packaging innovations, and new interconnect paradigms.

Erik Hosler observes, “It’s going to involve innovation across multiple different sectors.” This insight reflects the reality of scaling today. It is no longer about perfecting one technology; it is about aligning many.

The Essential Role of Advanced Materials

Advanced materials are among the most important EUV enablers. Photoresists must be engineered to manage high-energy photons while maintaining fidelity and low defectivity. Hard masks must be adapted to support complex pattern transfers. Etch chemistries must be developed to accommodate new substrates and multi-patterning steps.

Each of these innovations relies on partnerships between lithographers, chemical suppliers, process engineers, and toolmakers. When even one element in this chain falls short, the entire process window narrows, jeopardizing yield and performance. Materials science is no longer a supporting player. It is a central pillar of chip scaling.

Software and Simulation: Hidden Engines of Progress

Scaling also increasingly depends on how impeccably design and manufacturing processes are simulated before actual fabrication begins. Tools like optical proximity correction, process simulation, and design rule checking now play a critical role in lithographic success.

As EUV systems become more complex, machine learning and AI-based solutions are being used to predict variability, optimize mask designs, and identify yield-limiting factors. This computational layer allows engineers to anticipate issues early, reducing costs and improving first-time-right designs. In today’s ecosystem, software is just as essential as hardware.

Packaging and Photonics Extend the Benefits

Another way to supplement the EUV’s role is through advanced packaging. Techniques such as chiplet architectures, interposers, and 3D stacking allow chipmakers to mix and match functions on different dies, bypassing the need to integrate everything on a single monolithic chip.

Photonics becomes particularly important in this context. Optical interconnects reduce power consumption and increase bandwidth, especially in data-intensive applications like AI and cloud computing. Integrating photonics requires precision packaging and new materials—all of which must align with lithographic capabilities. Together, these elements allow for performance scaling even when transistor scaling slows.

Logic Versus Memory: EUV’s Differing Roles

EUV’s effectiveness also varies across different segments of chip design. In memory, where patterns are repetitive, EUV has delivered solid benefits and replaced older multi-patterning techniques. In logic, however, layout irregularity and variability make EUV adoption more challenging.

To address these issues, hybrid lithography approaches, combining EUV with DUV, multiple masks, or directed self-assembly, are being explored. Logic scaling increasingly depends on a mosaic of patterning strategies, where EUV is important but not dominant.

Workforce Readiness and Education

The shift toward multi-sector innovation means that the next generation of engineers must be trained in multiple fields. Lithography expertise alone is no longer enough. Designers must understand materials science, optics, system-level architecture, and software.

Universities and corporate training programs are adapting by offering interdisciplinary curricula and hands-on experience with cross-functional tools. Internships, consortia partnerships, and industry fellowships help bridge the gap between academia and application. The workforce that will extend Moore’s Law must think broadly, move flexibly, and collaborate instinctively.

Measuring Success in a Multi-Tool Era

If EUV alone cannot define the roadmap, then new success metrics are needed. Rather than focusing solely on transistor density, the industry is shifting to system-level indicators like energy per operation, total latency, performance per watt, and integration flexibility.

These metrics better reflect how products function in the real world. They reward synergy between technologies and encourage problem-solving at the system level. In this context, progress is not how small you can print but how well everything works together.

EUV’s Place in the New Semiconductor Mindset

As important as EUV is, the focus must stay on outcomes, not just tools. The measure of progress is not whether EUV can reach 0.55 NA, but whether it enables systems that serve people more efficiently.

This broader view of innovation reflects a key shift across the semiconductor industry. EUV is no longer the lone driver of progress. It is part of a larger, interconnected effort where breakthroughs in multiple sectors work together to keep scaling viable. The age of single-tool dominance has passed. What lies ahead is defined by ecosystems, platforms, and coordinated innovation.

Scaling as a Shared Responsibility

EUV lithography represents one of the greatest technical achievements in semiconductor history and is a cornerstone of modern manufacturing. But scaling today is not about one breakthrough; it is about many.

The challenge and opportunity lie in coordinating those breakthroughs. Material science, photonics, packaging, software, and design all have critical roles to play. Each advance must support and reinforce the others. That is how Moore’s Law will continue, not through singular brilliance but through shared ingenuity. The future of chips will be built by many hands working together.